1. Field of the Invention
The present invention relates to a memory device and, in particular, to a source-side-injection Electrically Erasable Programmable Read Only Memory (EEPROM) device based on a Flash cell which employs a sidewall polysilicon spacer as an Erase Gate (EG).
2. Discussion of the Prior Art
In order to realize a Flash EEPROM array having a density of 16 Mbits or higher, technology innovations in both memory cell structure and array architecture are required. In the past, Intel's well-know "T-shaped" ETOX cell has been intensively utilized in Flash memory applications because of its small cell size and simple stack gate structure. Examples of such devices are described by Jinbo et al., "A 5V-Only 16 Mb Flash Memory with Sector Erase Mode", IEEE JSSC, P. 1547, 1992 and by Atsumi et al., "A 16 Mb Flash EEPROM with a New Self-Data-Refresh Scheme for a Sector Erase Operation", IEEE JSSC, P. 461, 1994. However, the conventional operation issues, such as high programming current and high erase band-to-band tunneling current place severe limitations on the power supply (V.sub.cc) scalability and cell size scalability. In fact, band-to-band tunneling current limits V.sub.cc scaling in an ETOX memory array with a large sector size (i.e. 512K bits per sector) architecture. Furthermore, band-to-band tunneling current limits cell size scaling because a source junction as deep as 0.2 um is required for a 0.35 um technology. That means source lateral diffusion takes more than one third of the transistor channel length and cell scalability is severely limited.
Source side injection Flash memory cells using a polysilicon sidewall spacer as a select gate are introduced to address the high programming current issue associated with the ETOX cell. Examples of such devices are described by Wu et al., "Electrically Programmable Memory Device Employing Source Side Injection", U.S. Pat. No. 4,794,565, 1988 and by Naruke et al., "A New Flash-Erase EEPROM Cell with a Sidewall Select-Gate on its Source Side", IEEE IEDM, P. 603, 1989. However, an individual polysilicon-sidewall-spacer line has to be strapped with a metal line in order to be switched as a word line during a read cycle and thus, memory array layout becomes metal pitch limited. Furthermore, the issue of high band-to-band tunneling current during erase was not addressed.
Jeng et al., "Single Transistor Non-volatile Electrically Alterable Semiconductor Memory Device with a Re-crystallized Floating Gate", U.S. Pat. No. 5,067,108, 1991, proposed a source-side-injection Flash cell with a non-self-aligned select transistor. This cell is erased by a poly-to-poly tunneling mechanism and thus, band-to-band tunneling current is eliminated. With this approach, an independent select transistor with a silicide gate is used to replace the sidewall spacer select transistor and thus, metal strapping is not necessary. However, this cell has two transistors in series plus a source coupling region and thus, cell size is inherently large. Furthermore, the select gate channel length is alignment sensitive and the source junction has to sustain a high voltage, both of which undesirably limit further cell scaling.
Yuan et al. disclosed two U.S. Pat. Nos. 5,712,179 and 5,534,456 describing new EEPROM devices based on a split gate flash cell in a contactless virtual ground array. By eliminating metal contacts within memory cells, a compact flash memory array can be achieved. However, continuous source/drain bit lines introduce high bit line diffusion capacitance as well as high bit-line/word-line overlap capacitance and thus, slow down the memory access speed. Furthermore, the high programming current (&gt;300 uA/cell) associated with the ETOX-type programming mechanism, limits cell's Vcc scalability. Consequently, although Yuan's memory arrays are suitable for low speed, high density applications such as compact flash cards, they are not designed for the high speed, low Vcc, low power applications targeted in the present invention.